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An image sensor comprising an array of apertures each with its own local integrated optics and pixel array is presented. A lens focuses the image above the sensor creating overlapping elds of view bet...
We describe a programmable digital camera sensor with pixel-level analog-to-digital conversion (ADC). The sensor, which was designed and implemented by our group, is programmable in the sense that the...
Stanford University is developing a controlled reception pattern antenna (CRPA) array with beam research testbed to evaluate CRPA algorithms and software tools, and their effects on GPS signals and sa...
Advances in solid-state technology have enabled the development of silicon photomultiplier sensor arrays capable of sensing individual photons. Combined with high-frequency time-todigital converters (...
In traditional four-stage pipeline structures for H.264 video encoder hardware implementation, rate distortion optimization (RDO) based mode decision was turned off, and dual-port or ping-pang on-chi...
This paper proposes a hardware friendly multiresolution motion estimation algorithm and VLSI architecture for high definition MPEG-like video encoder hardware implementation. By parallel searching and...
Motion compensation (MC) is one of the most important technologies capable of removing the temporal redundancy and widely adopted by the main video standards. From the older MPEG-2 to the latest H.264...
In AVS-P2 video compression standard, similar to MPEG-2, entropy coding firstly assembles two dimensional coefficients of each block into a sequence of (Run, Level) combinations serially. As we know,...
Motion estimation is the most computational intensive part of H.264 video coding. The motion estimation of H.264 includes int eger motion estimation and fractional motion estimation. In this paper, a ...
With the improvement of network bandwidth, multimedia services based on streaming live media have gained much attention recently, among which IPTV has become a hot topic. After emergence of Peer-to-Pe...
In the advanced Audio Video coding Standard (AVS), many efficient coding tools are adopted in motion compensation, such as new motion vector prediction, direct mode matching, variable block-sizes etc....
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder.
!aIn this paper, we present a VLSI design of Variable Length Code Decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode Fixed Length Code, unsigned or signed k-th Exp-...
AVS is Chinese new audio and video coding standard. A pipeline-based architecture of inverse quantizer for AVS video standard is proposed in this paper. Due to using one-pass processing for Run Length...
The video coding standard H.264/AVC has adopted variable block size motion estimation to improve coding efficiency, which has brought heavy computation burden.The FFSBM (fast full search block matchin...

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